VLSI Design Engineer

Speedata is modernizing analytics infrastructure with the first purpose-built ASIC processor, the Analytics Processing Unit (APU), for analytics and AI data workloads. Delivering up to 100x faster Apache Spark performance while cutting infrastructure TCO by 90%, the APU executes analytics operations directly in silicon with seamless integration and no code changes.

Qualifications

• BSc in Electronics Engineering.

• 7+ Years of industry experience in VLSI Design.

• Acquaintance with all aspects of chip development.

• Familiar with Design/Verification tools and methodologies.

• Experience with Verilog RTL coding and Verification support.

• Experience with Synthesis flows – an advantage.

• Highly Motivated, Independent and responsible.

• Team Player and with excellent interpersonal skills.

• Expirience with DDR IPs - An Adavantage

• Expirience with DDR 5 and up IPs - A Huge Adavantage